1. Technical Field
The invention relates to an improved semiconductor integrated circuit. More specifically, the invention relates to the output stage of a semiconductor integrated circuit. Still more specifically, the invention relates to a semiconductor integrated circuit output stage with improved noise characteristics. Still more specifically, the invention relates to the phased driving of different channels of a parallel data bus.
2. Description of Related Art
Digital logic circuits and digital data transmission circuits are widely used in the areas of electronics, computer, and telecommunications equipment and peripherals. For example and without limitation, it is well known in the art that a computer is made up of individual integrated circuit chips connected together on a printed circuit board. Data flows between the individual integrated circuits as part of the inherent functioning of the computer. If this data is corrupted by noise, then the computer will malfunction. Similarly, a microcontroller circuit for driving a stepping motor or other electro-mechanical system will also often be made up of a number of integrated circuit chips connected by data busses. Driving data down these busses can be a source of noise if care is not taken to minimize the transient power.
A common trend across the field of digital electronics is an increase in the data flow, both in terms of clock rate and in terms of volume of data per clock cycle. This trend gives rise to several design challenges, including an increase in the number and density of in/out connections. Valuable silicon area can be wasted if too much space is devoted to connectivity. Another design challenge associated with higher clock frequencies is the trend towards increased radiation, where power leaves the signal line and becomes background noise.
Currently, integrated circuit packages contain numerous output driving pins which all simultaneously fire on a single clock edge. Referring to FIG. 1 a known N-pad output stage for a simultaneously switching output driver of a digital circuit is shown. N output digital signal lines 101 are connected to N flip-flops 102 whose clocks 103 are connected to a write-clock signal 104. The write-clock signal simultaneously triggers the array of N flip-flops 102. The outputs of the flip-flops are connected to buffers 105 that are connected to input/output pads 106. The output signals are latched by the flip-flop circuitry, which may be, but are not limited to, type D flip-flops. It should be noted, however, that, as is well known in the art, type D flip-flops fire the output upon the enable clock stroke. In this way synchronicity is maintained and clock race problems are reduced. Thus the enable signal triggers the output signals through the gates. The buffers act to amplify the power of the output signal in order to drive a transmission line, load or multiple loads. The write-clock signal enables each of the flip-flops simultaneously, in a synchronous manner. This signal sends the output data to the buffers, and thus to the parallel data bus at the same instant in time.
Associated with this synchronous firing is a deleterious amount of conductive, inductive and radiative electrical noise. As the number of output driving pins grows, so does the level of this noise. This excessive supply noise can and will cause the integrated circuit devices to malfunction in several ways. Loss of data, bad input levels and bad output signaling are among the many failure mechanisms aggravated by supply noise. Therefore it would be advantageous to have an improved integrated circuit output driver with improved noise characteristics, with lower peak powers, lower power consumption and with an efficient use of chip area which reduces the number of output pads.
The present invention overcomes the foregoing problems and allows for an improved flow of output data signals with low noise, low power consumption, and efficient use of the number of pads.
Improved performance is accomplished by routing the data down a parallel data bus in a definitely skewed manner, so that the N lines of a data bus are each driven at different phases of a clock cycle. For example, the data is held in a parallel array of flip-flops which leads to a parallel data bus. These flip-flops are triggered, or enabled, in a synchronously skewed manner by clocking signals that arrive at the flip-flops in a staggered manner. These clocking signals could be derived from a high frequency internal clock whose toggle rate is some multiple of the maximum output toggle rate. This invention has application in microcontrollers and in other communication and power applications.